An interconnect circuit board is the physical realization of electronic circuits or subsystems from a number of extremely small circuit elements electrically and mechanically interconnected on a substrate. It is frequently desirable to combine these diverse type electronic components in an arrangement so that they can be physically isolated and mounted adjacent one another in a single compact package and electrically connected to each other and/or to common connections extending from the package.
Complex electronic circuits generally require that the circuit be constructed of several layers of conductors separated by insulating dielectric layers. The conductive layers are interconnected between levels by electrically conductive pathways through the dielectric called vias. Such a multilayer structure allows a circuit to be more compact.
One well known method for constructng a multilayer circuit is by sequentially printing and firing thick film conductors and insulating dielectrics on a rigid insulative substrate such as alumina. The alumina substrate provides mechanical support and also X-Y dimensional stability and facilitates registration to the patterned thick film conductors and dielectric layers. However, the thick film process has a disadvantage in that printing through a screen mesh can result in pinholes or voids in the dielectric layer which can cause shorting between conductor layers. If a thick film dielectric is formulated to allow sufficient flow of the paste during the printing operation and thus to minimize the tendency to form pinholes, then the maintenance of small vias is likely to be compromised by the flow of dielectric paste into the via hole. Also, the repetitive printing and firing steps for each layer are time consuming and expensive.
Another prior art method for constructing multilayer circuits is that of co-firing a multiplicity of ceramic tape dielectrics on which conductors have been printed with metallized vias extending through the dielectric layers to interconnect the various conductor layers. (See Steinberg, U.S. Pat. No. 4,654,095.) These tape layers are stacked in registry and pressed together at a preselected temperature and pressure to form a monolithic structure which is fired at an elevated temperature to drive off the organic binder, sinter the conductive metal and densify the dielectric. This process has the advantage that firing need only be performed once, thus saving fabricating time and labor and limiting the diffusion of mobile metals which could cause shorting between conductors. However, this process has the disadvantage that the amount of shrinkage which occurs on firing may be difficult to control. This dimensional uncertainty is particularly undesirable in large complex circuits and can result in misregistration during subsequent assembly operations.
On the other hand, Vitriol and Brown in U.S. Pat. No. 4,645,552 disclose a process for constructing a multilayer circuit on a rigid substrate which is similar to the thick film process described above in the way that circuit layers of conductors and dielectrics are sequentially added to the circuit and fired. The circuit is fabricated on a rigid, dimensionally stable substrate by a sequence of steps such as the following:
(a) forming a conductor pattern on a dimensionally stable substrate; PA0 (b) forming via holes in a dielectric green tape; PA0 (c) laminating the green tape onto the substrate in registry with the conductor patterns; PA0 (d) firing the substrate, conductor and green tape; PA0 (e) metallizing the top surface of the dielectric tape and filling the vias; and PA0 (f) repeating steps (b) through (e) until the multilayer structure is complete. PA0 (a) providing a dimensionally stable electrically insulative substrate; PA0 (b) applying to the substrate a patterned conductive layer; PA0 (c) laminating to the patterned conductive layer and exposed areas of the substrate a layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (b); PA0 (d) filling the vias in the laminated green tape with a conductive metallization; PA0 (e) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequenece of steps (b) through (d) until the desired number of circuit layers has been obtained; PA0 (f) co-firing the multilayer assemblage from step (e); PA0 (g) applying a patterned conductive layer to the ceramic tape side of the co-fired assemblage from step (f) in registration with the vias in the ceramic tape; and PA0 (h) firing the patterned conductive layer. PA0 (a) providing a dimensionally stable electrically insulative substrate; PA0 (b) applying to the substrate a patterned conductive layer; PA0 (c) laminating to the patterned conductive layer and exposed areas of the substrate a layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (b); PA0 (d) filling the vias in the laminated green tape with a conductive metallization; PA0 (e) applying a patterned conductive layer to the green tape side of the unfired assemblage from step (d) in registration with the vias in the green tape. PA0 (f) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (c) through (e) until the desired number of circuit layers has been obtained; and PA0 (g) co-firing the multilayer assemblage from step (f). PA0 (a) providing a dimensionally stable electrically insulative substrate; PA0 (b) applying to the substrate a patterned conductive layer; PA0 (c) laminating to the patterned conductive layer and exposed areas of the substrate of layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (b); PA0 (d) filling the vias in the laminated green tape with a conductive metallization; PA0 (e) applying a patterned conductive layer to the green tape side of the unfired assemblage from step (d) in registration with the vias in the green tape; PA0 (f) laminating to the patterned conductive layer and exposed dielectric areas a layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (e); PA0 (g) in the event the multilayer circuit requires more than three layers having conductive patterns, repeating the sequence of steps (d) through (f) until the desired number of circuit layers has been obtained; PA0 (h) co-firing the multilayer assemblage from step (g); PA0 (i) filling the vias in the fired ceramic tape and applying to the ceramic tape side of the fired assemblage from step (h) a patterned conductive layer in registration with the vias in the ceramic tape; and PA0 (j) firing the multilayer assemblage from step (i). PA0 (a) providing a dimensionally stable substrate; PA0 (b) laminating to the substrate a layer of dielectric green tape; PA0 (c) filling any vias in the green tape and applying to the layer of dielectric green tape a patterned conductive layer; PA0 (d) laminating to the patterned conductive layer and exposed areas of the underlying dielectric green tape a layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (c); PA0 (e) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (c) and (d) until the desired number of circuit layers has been obtained; PA0 (f) co-firing the multilayer assemblage from step (e); PA0 (g) filling the vias in the fired ceramic tape and applying a patterned conductive layer to the ceramic tape side of the fired assemblage from step (f); and PA0 (h) firing the vias and patterned conductive layer from step (g). PA0 (a) providing a dimensionally stable substrate; PA0 (b) laminating to the substrate a layer of dielectric green tape; PA0 (c) filling any vias in the green tape and applying to the layer of dielectric green tape a patterned conductive layer; PA0 (d) laminating to the patterned conductive layer and exposed areas of the underlying dielectric green tape a layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (c); PA0 (e) filling the vias in the dielectric green tape and applying to the layer of dielectric green tape from step (d) a patterned conductive layer; PA0 (f) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (d) and (e) until the desired number of circuit layers has been obtained; and PA0 (g) co-firing the multilayer assemblage from step (f). PA0 (a) providing a dimensionally stable substrate; PA0 (b) laminating to the substrate a layer of dielectric green tape; PA0 (c) filling any vias contained in the dielectric green tape layer; PA0 (d) applying to the layer of green tape a patterned conductive layer in registry with any vias contained in the underlying dielectric green tape layer; PA0 (e) laminating to the patterned conductive layer and exposed areas of the underlying green tape a layer of dielectric green tape having vias formed therein, the vias being in registration with the patterned conductive layer of step (d); PA0 (f) filling the vias contained in the dielectric green tape layer applied in step (e) with a conductive metallization; PA0 (g) in the event the multilayer circuit requires more than two layers having conductive patterns, repeating the sequence of steps (d) through (f) until the desired number of circuit layers has been obtained; PA0 (h) co-firing the multilayer assemblage from step (g); PA0 (i) applying a patterned conductive layer to the ceramic tape side of the cofired assemblage from step (h) in registration with the vias in the ceramic tape; and PA0 (j) firing the patterned conductive layer.
Such a process eliminates some of the disadvantages of the thick film multilayer circuit fabrication process because the risks of pinholes and via closure are eliminated due to the fact that green tape is used as a dielectric insulating layer and mechanically punched vias are employed. However, the process requires that a separate firing step be included for each layer of dielectic tape. This is time consuming and expensive. Furthermore, each additional firing increases the likelihood of conductor diffusion into the dielectric layers and concomitantly the risk of shorting between conductor layers.
A still further method for fabricating multilayer circuits using green tape is disclosed in Rellick, U.S. Pat. No. 4,655,864 in which firing of the functional layers is carried out sequentially, i.e., each layer is fired before application of the next layer.